Embodiments of the present invention relate to the field of built-in self-test (BIST)for logic circuits. More particularly, embodiments of the present invention relate to deterministic BIST.
The power and complexity of computer systems and other digital electronic devices are continually increasing, along with the level of integration of integrated circuit devices.
As the power and complexity of logic circuits increase, the volume of test data that must be applied to functionally verify a circuit, and the number of responses that must be evaluated to fully test a circuit increase as well.
At the same time the test data volume is increasing, higher levels of integration have restricted access to possible test points in the circuits. For example, the number of transistors in digital integrated circuits has increased much more rapidly than the pin counts of the packages in which they are housed. As a result, the circuit interface becomes a bottleneck for the application and evaluation of test data. The challenge of circuit testing is magnified at the board and system level as several integrated circuits may be combined. The approximate cost of testing increases by an order of magnitude with the step from chip to board, and from board to system.
Traditionally, automatic test equipment (ATE) has been used to generate test input data and evaluate the response of the circuit under test (CUT), or device under test (DUT). In order to cope with the challenge of testing increasingly complex circuits, built-in self-test (BIST) has been developed.
In BIST, circuits dedicated to testing are combined with the CUT or DUT in order to avoid the problems of external application and extraction of test data, and reduce the cost of the ATE required. There are three general BIST schemes that are currently in use for test pattern generation: exhaustive/pseudo-exhaustive testing, pseudo-random testing, and deterministic testing.
In an exhaustive testing scheme, all possible input patterns are applied to the DUT. For an n-input combinational logic circuit, 2n patterns are required. Exhaustive testing will detect all irredundant faults, but the time required for testing becomes prohibitive with a large value for n. These systems are generally not commercially feasible.
Pseudo-exhaustive testing can be used to extend the applicability of exhaustive testing by partitioning the DUT into several subcircuits. However, for VLSI circuits, it may be difficult to apply a partitioning scheme that will sufficiently reduce the number of inputs to a given partition.
Pseudo-random testing uses the application of pseudo-random test patterns generated by a pseudo-random pattern generator (PRPG) such as a linear feedback shift register (LFSR) in place of truly random sequences. Although an LFSR is relatively straightforward in implementation, tradeoffs must be made between the number of test patterns, degree of fault coverage, and the handling of random pattern resistant faults.
Since random patterns have an equal probability for a test bit being a xe2x80x9c0xe2x80x9d or a xe2x80x9c1,xe2x80x9d a random pattern test generators must generate a large number of patterns in order to produce sequences that are dominated by either a xe2x80x9c0xe2x80x9d or a xe2x80x9c1,xe2x80x9d as are required by random pattern resistant faults. The number of required patterns can be reduced somewhat by weighting the output of a pseudo-random pattern generator to skew the probability of a xe2x80x9c0xe2x80x9d or a xe2x80x9c1;xe2x80x9d however, the most effective approach is deterministic testing.
Deterministic testing involves the computing and storing of the input test patterns and the corresponding output responses on the DUT. Automatic test pattern generators (ATPG) are used to compute the test vectors. This method is more direct than pattern generation and can be used to target specific faults, but the overhead is extremely high due to on-circuit storage requirements.
Pseudo-random and deterministic testing techniques can be combined in BIST architectures such as Self-Testing Using an MISR (multiple input signature register) and Parallel Shift Register Sequence Generator (STUMPS.) STUMPS is the most commonly used logic BIST in use today. The basic structure used to test circuitry is an LFSR that feeds pseudo-random data through parallel chains (called channels) that are each associated with a section of the DUT. The responses are captured in the channels and scanned out into a MISR and compacted. In addition to generating pseudo-random patterns, the LFSR may also be loaded with specific initial values (seeds) that are derived on the basis of a set of required deterministic test patterns, which are found within the output of the LFSR once the proper seed is loaded.
Typically, an LFSR will be cycled many times in order to generate a large set of pseudo-random test patterns. In addition to the pseudo-random phase of testing, the LFSR will be seeded in order to produce deterministic bit sequences. Due to constraints on the composition of the deterministic test patterns, the seeds used for generation of the deterministic patterns can only be used for a relatively small number of cycles, and a number of seeds are usually used to provide a complete test pattern, with each seed providing the same number of bit sequences to the channels.
Although the STUMPS architecture has been used to improve the efficiency of BIST by combining pseudo-random and deterministic testing, the conventional practice of using each deterministic seed to provide a fixed number of bit sequences fails to maximize the efficiency of deterministic testing using STUMPS. This is in part due to the variability of the test patterns and their associated needs of values in scan cells.
Accordingly, embodiments of the present invention provide a method for improving the efficiency of deterministic testing using a variation of the STUMPS architecture. Embodiments of the present invention improve the performance of built-in self-test (BIST) by using a plurality of seeds with variable lifetimes (clock cycles) for deterministic test pattern generation.
A system and method for time slicing deterministic patterns for reseeding in logic BIST is disclosed. The known properties of a linear feedback shift register (LFSR) and an associated set of channels are used in conjunction with a desired deterministic test pattern to create one or more seeds which can be used by the LFSR to generate the test pattern. The test pattern can be divided into a number of segments, with each segment having approximately the same number of xe2x80x9ccarexe2x80x9d bits. The segments can be varied in length. The segments can be visualized as having rows of bits that span the set of channels. In one embodiment, the number of shifts required to fill a segment using a particular seed is stored along with the seed as a lifetime tag. During testing, each deterministic test pattern is generated by loading a seed into the LFSR and cycling the LFSR in accordance with the tag of that seed.
In an embodiment of the present invention, a modified STUMPS architecture having an LFSR, phase shifter, channel array, compactor, and a MISR is used to apply deterministic test patterns to a logic circuit. The deterministic patterns are generated by seeding the LFSR with a predetermined seed and cycling the LFSR for a prescribed number of times. The number of times that the LFSR is cycled for each seed is determined by the number of targeted xe2x80x9ccare bitsxe2x80x9d that are required by the test pattern(s) that can be encoded into a seed. This is dependent upon the length of the LFSR, and the desired probability of obtaining a system of independent equations for solution. The value of the seed and its associated lifetime are determined, in one implementation, by an ATPG process and systems of equations.
Another embodiment of the present invention includes automated test equipment (ATE) for testing circuits at the chip, board or system level. The ATE comprises a storage medium for optionally storing deterministic patterns seeds and their associated lifetime tags; a medium for optionally storing data output signatures; a computer for programmed test control; and, an interface to a circuit under test.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.